`timescale 1ns/1ns
module temperature_tb(); 

reg         clk;
reg         rst_n;
reg         dq_in;
reg  [4:0]  sw;

defparam  inst_top.inst_ds18b20_driver.TIME_750ms = 37500,
            inst_top.inst_ds18b20_driver.TIME_375ms = 18_750,
            inst_top.inst_ds18b20_driver.TIME_187_5ms = 9_375,
            inst_top.inst_ds18b20_driver.TIME_93_75ms = 4_688;

top   inst_top (
    .clk(clk),
    .rst_n(rst_n),
    .sw(sw),
    .dq_in(dq_in)
);  

initial begin
    clk = 0;
    rst_n = 1;
    #200;
    rst_n = 0;
    #40;
    rst_n = 1;
end

always #10 clk = ~clk;

initial begin
    dq_in = 0;
    sw = 5'b00111;
end
endmodule